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Senior Low Power DFT Engineer

Job Description

We are looking for an experienced R&D engineer to architect, design and verify the design-for-testing infrastructure of our next generations of chips.

To be in close relationship with SoC architects and the whole IC design team.

This position requires numerous collaborations with the different departments of the Group (internal and external to the site): IC design, Boards, Embedded software, Application

***Requirements and responsibilities***

  • Specify DFT architecture and insertion: scan (stuck-at, at-speed, scan compression), memory BIST
  • Implement and verify the DFT in the chips
  • Define the chip power intent (UPF) for physical implementation
  • Optimize DFT to minimize impact on functional mode (timings, power)
  • Support physical implementation engineers for aspects related to DFT and to low-power checks
  • Generate and verify (simulation) test patterns
  • Optimize test coverage and test time
  • Support test engineers on test program setup and debug on industrial tester

***What you will need***

  • DFT techniques and associated EDA tools (e.g. Modus )
  • Proficiency in UPF format
  • LP checks and associated tools ( e.g. Conformal LP )
  • Efficient use of simulation tools (RTL, netlist, back-annotated netlist)
  • Ability to work autonomously and proactively on assigned tasks
  • Strong team spirit and communication, happy to collaborate and share with his teammates, even remotely. Eager to share skills and advice, eager to learn new skills
  • Work comfortably in an international environment, exchanging by e-mail, telephone or conf-calls