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Senior Digital Verification Engineer

Job Description

We have a current opportunity for a Senior Digital Verification Engineer on a permanent basis. The position will be based in Valencia. For further information about this position please apply.

Profile Educational Background:

-University degree in Electronics or related

-10 years experience in digital design/verification with hands-on experience on relevant design/simulation tools

-Knowledge of design verification methodologies, tools, and languages (UVM, SystemVerilog, assertions …)

-Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices.

-Experience with FPGA is a plus.

-Knowledge of backend flow tools for design synthesis, timing sign-off, and power analysis

-Team oriented, committed to deadlines and development discipline

-Communication skills and proficiency in English Position

Focus / Areas of Responsibility:

-Verification of integrated mixed-signal and digital blocks and CMOS IC's

-Creation of verification plans for complex mixed-signal or digital devices

-Development of verification environment and ensure proper verification coverage for enabling bug-free silicon manufacturing.

-Creation of DV test cases and debugging of simulation results Design of digital blocks at RTL level and addition of DfT concept onto the design.

-Creation and patenting of new IP Synthesis and timing sign-off for on-silicon implementation.