We have a current opportunity for a Principal Digital Design Verification Engineer on a permanent basis. The position will be based in Villach( Austria). For further information about this position please apply.
- Building Verification plans.
- Verification plan execution, tracking, and documentation.
- Selecting the right verification methodology
- Executing tests in these environments on RTL and gate-level.
- Sciences degree in Electrical Engineering, Information Technology, Telematics or comparable with focus on electronics
- 7+ years of experience in pre-silicon verification
- Good project experience with SV-UVM/ Specman e
- Good knowledge of VHDL, (System)Verilog
- Knowledge of property checking, mixed-signal verification is a plus
- Solid Unix programming languages, e.g. Shell, Perl, TCL
- Fluent English skills with German skills as a plus.