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Digital Verification Engineer

Job Description

We have a current opportunity for a Digital Verification Engineer on a permanent basis. The position will be based in San Francisco. For further information about this position please apply.

RESPONSIBILITIES:

- Verify with SystemVerilog and reusable, standardized methodologies. Verify digital systems that use both custom and standard IP components and interconnects. Microprocessor cores and hierarchical memory subsystems.

- Assist in verification and modeling at the chip top level.

-Debug tests with design engineers to deliver functionally correct design blocks. Work closely with the design and test teams to define test specifications, verification plans, and manufacturing transfer.

- Analyze coverage metrics and establish verification best practices.

REQUIREMENTS

TITLE:

- MSc in Electronic, Electrical, Computer Engineering or relevant field.

REQUIRED EXPERTISE:

- AT LEAST 3 YEARS in similar tasks.

DESIRABLE :

Knowledge & Skills:

- Experience in the verification of designs such as transceivers ICs and System on Chip (SoC).

- Industry-standard simulators, revision control systems, and regression systems.

- Verilog, SystemVerilog, SVA.

- Scripting languages, such as Perl or Python.

- UPF flow.

- Familiarity with SoC standard interfaces (e.g. AHB, APB) and memory system architectures.

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