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Digital Validation Engineer

Job Description

We have a current opportunity for a Digital Verification Engineer on a permanent basis. The position will be based in Munich and working remotely is an option. For further information about this position please apply.

RESPONSIBILITIES:

- Verify with SystemVerilog and reusable, standardized methodologies.

-Debug tests with design engineers to deliver functionally correct design blocks. Work closely with the design and test teams to define test specifications, verification plans, and manufacturing transfer.

- Analyze metrics and establish verification best practices.

REQUIREMENTS

TITLE:

- MSc in Electronic, Electrical, Computer Engineering or relevant field.

REQUIRED EXPERTISE:

- AT LEAST 2 YEARS in similar tasks.

DESIRABLE :

Knowledge & Skills:

- Experience in ICs and SoC.

- Verilog, SystemVerilog, SVA.

-Perl or Python.

- UPF flow.

- Familiarity with SoC standard interfaces (e.g. AHB, APB) and memory system architectures.

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