We have a current opportunity for a Digital Verification Engineer on a permanent basis. The position will be based in Munich and working remotely is an option. For further information about this position please apply.
- Verify with SystemVerilog and reusable, standardized methodologies.
-Debug tests with design engineers to deliver functionally correct design blocks. Work closely with the design and test teams to define test specifications, verification plans, and manufacturing transfer.
- Analyze metrics and establish verification best practices.
- MSc in Electronic, Electrical, Computer Engineering or relevant field.
- AT LEAST 2 YEARS in similar tasks.
Knowledge & Skills:
- Experience in ICs and SoC.
- Verilog, SystemVerilog, SVA.
-Perl or Python.
- UPF flow.
- Familiarity with SoC standard interfaces (e.g. AHB, APB) and memory system architectures.