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ASIC Verification Engineer

Job Description

Our client is currently looking for an experienced ASIC Verification Engineer to join their dynamic enthusiastic circuit design team.
As a member of the circuit design team, you will actively contribute to the verification of our next generations of chips:

***Requirements and responsibilities***

● Building up of verification plan in relation with SoC architects and designers: features to be tested, test strategy, target coverage, description of tests and conformity matrix;
● Setup of testbenches (SystemVerilog/UVM) at IP, subsystem and/or top chip levels;
● Interfacing with software team for specific embedded SW developments required for test;
● Implementation and execution of planned tests, analysis of results and report of encountered bugs;
● Continuous improvement of verification environments: packaging of in-house verification IPs for reuse on different testbenches, automation of tests and non-regression procedures, etc.;
● Interfacing with the design team for analysis and fixing of bugs;
● Associated documentation.

***What you will need***

● Command of ASIC verification methods and techniques, preferably using UVM;
● Skills in corner case-driven, coverage-driven and possibly formal verification;
● RTL simulation and debug using EDA tools (e.g. NCSim, Xcelium);
● Knowledge of usual EDA scripting languages (TCL, Bash, Makefile);
● C programming in embedded environments;
● Familiarity with versioning/revision control systems
● Liking for debug and problem solving;
● Good level of spoken and written English, to be used daily to communicate with colleagues and international partners
● Organizational skills;
● Strong team spirit and communication abilities
● Ability to work autonomously and proactively on assigned tasks.
● Master Degree or plus with a specialization in microelectronics;
● A first experience in RTL verification is mandatory, preferably using UVM methodology;
● Experience in other parts of ASIC design flow is a plus: design, RTL checks, synthesis, equivalence checking etc